1. Field of the Invention
This invention relates generally to timing circuits in a computer processor, and more particularly to an improved circuit and method for controlling asynchronous circuits, especially in multiprocessor arrays on a single chip.
2. Description of the Background Art
In the art of computing, speed is a much desired quality, and the quest to create faster and more efficient computers and processors is ongoing. The operation of digital logic circuits in computer processors is generally coordinated by a clock signal that ensures appropriate sequential functioning of the component parts. A common technique used in the art is to hold information in edge-triggered flip-flops that can change their output state at clock signal transitions, with enable gates controlling readiness of logic outputs. With this technique, state changes in storage elements occur synchronously, in increments of one clock period or integer multiples thereof, sequentially in time, and only within a very narrow time interval, for example at the leading edge of the clock.
As design systems grow in complexity and clock speeds increase, several limitations in synchronous design become more problematic. Some of such limitations include the need for a large number of transistors, high power consumption, and slow speeds due in part to what is known as designing for the “worst case performance.” In particular, clock distribution over a whole circuit consumes a lot of power because the clock and other circuit elements (e.g., clock buffers, latches, and combinational logic) are constantly operating, even at times when no useful function is being performed. Furthermore, because a synchronous circuit is driven with a constant clock rate, the clock period must be long enough to constantly comply with the worst case computation delay under worst case process, voltage, and temperature conditions. This ultimately leads to slower performance because processes that are completed have to wait for unfinished processes to be completed before they can begin a new process.
In efforts to avoid such limitations, circuit designers have begun to explore the benefits provided by asynchronously-operating systems. In asynchronously-operating systems, data transfer handshake signals and standard delays are two known methods used to enable sequential events to proceed at their actual pace rather than during a predetermined number of clock cycles. Accordingly, asynchronous circuits can have a speed advantage, require fewer transistors to implement, and need less operating power, as only the active circuits are operating at a given moment. Mixed designs are also known to those skilled in the art. Such designs utilize a clock in parts of the circuit, and asynchronous features in others.
Although asynchronously-operating systems provide several advantages over synchronously-operating systems, there are still several disadvantages to overcome. For example, subsystems within an asynchronous system communicate via handshakes, which leads to the need for additional circuitry and operations. As another example, the problem of mistiming between events is common because asynchronously-operating systems are not clock-driven, and therefore, do not operate in a predetermined time domain.
What is needed, therefore, is a system to overcome the problem of mistiming in next generation computer processors utilizing asynchronous features, especially in multiprocessor arrays used in single-chip embedded systems.